The MAC Card, Conceptually, performs only one operation-that of multiplying the inputs provided to it and accumulation within on-chip RAMs of the ASICs. It thus has only the multiplier chips and their associated logic as its constituents. Unlike the FFT and the Delay cards, there are no on-board RAMs and their associated circuitry. The aspect has greatly simplified its design. It can broadly be classified into the following sections :
1.The Input Section:
This is the largest section of the card apart from the multiplier chips. The card has total of 8 different inputs which form the 4 rows and 4 columns of a 4-by-4 matrix. The multiplier chips form the 16 nodes thus obtained. These 8 inputs are received from the FFT subsystem via a distribution system ( described later ) as ECL signals. This section thus has the ECL-to-TTL converters ( MC10125 ) which feed a set of latches ( 74F821 and 74F574 ) to capture the data on the card with the on-board clock. These data latches then feed the multiplier chips.
2.The Multiplier Chips:
The 16 multiplier chips are the FX ASICs operating in one of the three MAC modes viz, Non-polar, Polar or Indian Polar. Of these, the Indian Polar mode is the default operating mode while the Non-Polar is the most scarcely used mode. The Polar mode will be used whenever calculation of Stokes parameters is required. The Multipliers operate in parallel, accumulating the products till they are read-out. The read-out is time-multiplexed, with all the chips on the same bus. A chip select enables each chip and an address provided to it reads out a result. Since the result is 36-bit wide while the output port is only 18-bits wide, the result is read out in two parts. The real and imaginary parts of the complex number are read in two consecutive words. The common exponent is split into two parts of 3-bits each and is combined with the 15-bits real or imaginary a mantissa to form an 18 bit word. The LSB 3-bit of the exponent is combined with the real mantissa and the MSB 3-bits with the imaginary mantissa.
3.Control Circuitry:
This includes logic required for capture and distribution of clocks and the various control signals required by the ASIC in MAC mode. The clock is received as an ECL signal. It is then converted to TTL level ( by a MC10125 ) and distributed to all ASICs and other logic chips by a pair of clock drivers ( 74ACT11208 ). Of the two clock drivers, one provides clocks only to the ASICs where as the other to the latches ( 74F821, 74F574, 74F175, 74F824 which captures data and control signals ). The clocks from these two drivers differ from each other by an amount provided by the delay line MDLDL-TTL-10F required to provide sufficient setup time for the ASICs. The data read from the ASICs is latched at the card edge ( by 74F823 ) before transmitting it on the backpanel. The cards too, like the chips, are read out in a time-multiplexed fashion.